Guide to Computer Processor Architecture : A RISC-V Approach, with High-Level Synthesis by Bernard Goossens

This unique, accessible textbook presents a succession of implementations of the open-source RISC-V processor.? Implementations are offered in increasing difficulty (non-pipelined, pipelined, deeply pipelined,?multi-threaded, multicore). Each implementation is shown as a High-Level Synthesis (HLS) code?in C++.??This facilitates synthesis and testing?on an FPGA-based?development board (Such a board can be freely obtained from the Xilinx?University Program targeting university professors). The book can be useful for several reasons. First, it is a novel way to?introduce computer architecture: The codes given can serve as labs?for a processor architecture course. Second, the book content is based?on the RISC-V Instruction Set Architecture, which is an open-source?machine language promising to become the main machine language to be taught,?replacing DLX and MIPS. Third, all the designs are implemented through?the HLS tool, which is able to translate a C program into?an intellectual property (IP).? Lastly,?HLS will become the new standard for IP implementations, replacing Verilog/VHDL; already there are job positions tied to HLS, with the argument of rapid IP development. Hence, in addition to offering undergraduates a firm introduction, the textbook/guide can also serve engineers willing?to implement processors on FPGA, as well as researchers willing to develop?RISC-V based hardware simulators. Bernard Goossens?is Professor in the Faculty of Sciences at the Universit? de Perpignan, France.? He is author of the French-language book from Springer,?Architecture et microarchitecture des processeurs, 2002.
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